`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/03/15 18:10:06
// Design Name:
// Module Name: testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module testbench();
    reg clk, rst;
    
    wire 	jump;
    wire 	branch;
    wire 	alu_a_src;
    wire 	memtoreg;
    wire 	memwrite;
    wire 	regwrite;
    wire [1:0]	alu_b_src;
    wire [2:0]	extop;
    wire [3:0]	alu_ctr;
    wire [31:0] inst;
    wire [31:0] pc, pc_next_jump; 
    wire [31:0] imm, reg_data_1, reg_data_2;
    wire [31:0] alu_srcA, alu_srcB, alu_result;
    wire [31:0] reg_data_write;
    wire [31:0] mem_rdata;
   
    top u_top(
            //ports
              .clk( clk            		),
              .rst( rst            		),
              .mem_rdata(mem_rdata),
              .inst(inst),
              
              .jump(jump),
              .branch(branch),
              .alu_a_src(alu_a_src),
              .memtoreg(memtoreg),
              .memwrite(memwrite),
              .regwrite(regwrite),
              .alu_b_src(alu_b_src),
              .extop(extop),
              .alu_ctr(alu_ctr),
              
              .pc(pc),
              .pc_next_jump(pc_next_jump),
              .imm(imm),
              .reg_data_1(reg_data_1),
              .reg_data_2(reg_data_2),
              .alu_srcA(alu_srcA), 
              .alu_srcB(alu_srcB),
              .alu_result(alu_result),
              .reg_data_write(reg_data_write)
        );


    initial begin
        rst <= 1;
        #10;
        rst <= 0;
    end

    always begin
        clk <= 1;
        #2
         #8;
        clk <= 0;
        #2
         #8;

    end

    always @(negedge clk) begin
        if(memwrite) begin
            /* code */
            if(reg_data_2 === 32'hf000 ) begin
                /* code */
                $display("Simulation succeeded");
                $stop;
            end
            else begin
                /* code */
                $display("Simulation Failed");
            end
        end
    end
endmodule
